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Reblogged by cstanhope@social.coop ("Your friendly 'net denizen"):
azonenberg@ioc.exchange ("Andrew Zonenberg") wrote:
In loving memory of the Xilinx CoolRunner-II CPLD family (2002-2024). They had a long run but were the last major product term CPLD family on the market and the time finally came for them to go EOL.
These parts will always be a bit special to me because they were the first programmable logic family I did bitstream RE work on, as well as my first major gate-level silicon RE project.
As a tribute, here's a never-before-seen image of the XC2C384 (second largest device in the family), made on UMC 180nm like the others.
There's five outer power rings. Likely VCCINT, VCCAUX, GND, VCCO, and maybe something else? The second ring in from the outside looks to be VCCO (since it's broken at IO bank boundaries).
Center of the device is boot flash and global config, then above/below are two tiles of 2x3 function blocks for a total of 24 FBs, each with 16 macrocells. Global interconnect runs vertically down the center of the device.
Full res: https://siliconpr0n.org/map/xilinx/xc2c384/azonenberg_mit20x/
