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Reblogged by cstanhope@social.coop ("Your friendly 'net denizen"):

x4nw@cathode.church ("xan but witchy 🧙‍♀️👻🎃💜🖤") wrote:

let's say i wanted to use verilog to write a controller for some oldschool DRAM (EDO SIMMs specifically) for Reasons

let's also say i wanted some sort of verification model i can use in a testbench that will verify all my timings and throw an assertion if i violate any of a huge table of datasheet timing rules

does anyone have any good resources for how to actually approach this? I see a lot of really deep like journal article type things on verification technologies and not much else. how do people do this in a practical setting?