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Reblogged by cstanhope@social.coop ("Your friendly 'net denizen"):

PythonLinks ("Forth Co-Processor") wrote:

I will be speaking on Saturday Morning, Jan25th, at the SVFIG meetup about an #FPGA Vector processor. Here is how it does #vector multiplies. Starts at 9:30 am California time. #verilog

http://forth.org/zoom

Attachments:

• An image of two vectors being multiplied, and creating a third vector. Each element in the vector feeds a multiplier, which feeds the corresponding element in the results vector. The results vector has twice as many bits as the two arguments.