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taral ("JP Sugarbroad") wrote:
Thought of the day: What would #riscv look like if you made #CHERI integral?
1. CSRs could be "capability-mapped". No need for separate CSR instructions. This might be a win or a loss depending on your use case?
2. Traps could generate special sentry capabilities that encode complex execution state. I see a common pattern of per-mode "save" registers for traps. How much of that can we avoid with this? Is LDM/STM an option?
3. Instead of hidden extended registers, could we require pair support?