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Boosted by cstanhope@social.coop ("Your weary 'net denizen"):
CanLehmann ("Can Lehmann") wrote:
I can finally talk about what I did during the last year! In collaboration with @cfbolz we developed a Verilog simulator called verijit based on meta-tracing just in time compilers. The results are pretty crazy: verijit is up to 100x faster than verilator for simulating processors.
You can follow us on Mastodon @verijit
We have a neat mandelbrot demo below: